I suppose you are correct. If the bit isn't structural, it doesn't need to pass any test for microcracks. If it is structural and it passes testing, YOLO that shit.
It's just the core frames that need serious attention though. I don't think I have been around a single aircraft that wasn't constantly bleeding some kind of fluid, so everything else not related to getting the thing in the air and keeping it from completely disintegrating while in flight is mostly optional. (I am joking, but not really. Airplanes hold the weird dichotomy of being strangely robust and extremely fragile at the same time.)
I am curious as to why they would offload any AI tasks to another chip? I just did a super quick search for upscaling models on GitHub (https://github.com/marcan/cl-waifu2x/tree/master/models) and they are tiny as far as AI models go.
Its the rendering bit that takes all the complex maths, and if that is reduced, that would leave plenty of room for running a baby AI. Granted, the method I linked to was only doing 29k pixels per second, but they said they weren't GPU optimized. (FSR4 is going to be fully GPU optimized, I am sure of it.)
If the rendered image is only 85% of a 4k image, that's ~1.2 million pixels that need to be computed and it still seems plausible to keep everything on the GPU.
With all of that blurted out, is FSR4 AI going to be offloaded to something else? It seems like there would be a significant technical challenges in creating another data bus that would also have to sync with memory and the GPU for offloading AI compute at speeds that didn't risk create additional lag. (I am just hypothesizing, btw.)